1. Field of the Invention
The instant disclosure relates to a semiconductor structure and a fault location detecting system, and more particularly, to a semiconductor structure and a fault location detecting system for increasing the probability of generating reflected secondary electrons.
2. Description of Related Art
Each step in a memory manufacturing process has to undergo stringent quality control to produce a high and stable yield rate. When the yield rate drops below a normal standard, test engineers are called in to investigate the cause.
Bit-map memory test programs are one of the more commonly used programs to test physical memory. The testing parameters for the bit-map memory test program first have to be setup according to the physical address table provided by the memory manufacturer. The data output pattern from the memory test program is regarded as the electrical address, which is supposed to match the corresponding physical address in the physical memory. The output of the bit-map memory test program displayed on a screen is represented by a stream of 0 and 1 in a specific pattern.
During bit-map memory testing, test data is first written into the physical memory, and then the data is read out of memory. If the tested memory is a good memory chip, the results of the test program should correspond to the test data written into specified memory locations. If faulty memory addresses or memory cells exist in the physical memory, the data values at those memory locations cannot be read, causing the corresponding data image to be different from the data input into the memory. Through such comparison of FIB modeling results and the bit-map memory test results, whether or not the bit-map memory test detects all faulty memory address lines and data cells in a memory chip can thus be verified.
It is absolutely important that the physical memory address table provided by the memory manufacturer be a complete match with the physical memory address. Only then, can the memory test program based on the physical memory address table be successfully performed on the physical memory with high accuracy. It only takes a small data discrepancy in the physical memory to render the tested memory useless, because the test program is unable to test all physical memories to produce a clean test report. To prevent such errors during memory testing with the bit-map memory test program, a verification process is developed in the present invention by means of FIB (Focused Ion Beam) apparatus, which can tell how accurate and reliable a bit-map memory test program is.
Moreover, another way to test physical memory is the analysis of the passive voltage contrast. When the focused ion beams are projected onto a pre-test memory, the secondary electrons triggered by the FIB apparatus can be received to obtain image contrast value (shading value) of the pre-test memory, thus the fault location (the positions of bright and dark spots) can be detected by an electro microscope. However, the image contrast value on the NMOS area of the semiconductor structure can not be efficiently increased in the prior art.